\input{../slides/common/slides_common}

\newif\ifbook
\input{../shared/chisel}

\title{Software-Defined Hardware: Digital Design in the 21st Century with Chisel}
\author{Martin Schoeberl}
\date{\today}
\institute{Technical University of Denmark}

\begin{document}

\begin{frame}
\titlepage
\end{frame}

%\begin{frame}[fragile]{Welcome}
%\begin{itemize}
%\item You can also join this session via the Zoom app
%\item Probably better quality and more functions
%\item The link is in the Whova chat
%%\item \url{https://dtudk.zoom.us/j/61032875012}
%%\item Let us have an introduction round
%\item This shall be interactive: please join with video!
%\item You can ask questions by unmuting and just talking
%\item Use the chat in Zoom to ask questions
%\end{itemize}
%\end{frame}

% edited copy from unit1 and generation
\begin{frame}[fragile]{Motivating Example:\\
Lipsi: Probably the Smallest Processor in the World}
\begin{itemize}
\item Tiny processor
\item Simple instruction set
\item Shall be small
\begin{itemize}
\item Around 200 logic cells, one FPGA memory block
\end{itemize}
\item Hardware described in Chisel
\item Available at \url{https://github.com/schoeberl/lipsi}
\item Usage
\begin{itemize}
\item Utility processor for small stuff
% \item Could be used for your vending machine
\item In teaching for introduction to computer architecture
\end{itemize}
\item The design took place on the island Lipsi
\end{itemize}
\end{frame}

\begin{frame}[fragile]{The Design of Lipsi on Lipsi}
\begin{figure}
    \centering
    \includegraphics[scale=0.3]{lipsi}
\end{figure}
\end{frame}

\begin{frame}[fragile]{Lipsi Implementation}
\begin{itemize}
\item Hardware described in Chisel
\item Tester in Chisel
\item Assembler in Scala
\begin{itemize}
\item Core case statement about 20 lines
\end{itemize}
\item Reference design of Lipsi as software simulator in Scala
\item Testing:
\begin{itemize}
\item Self testing assembler programs
\item Comparing hardware with a software simulator
\end{itemize}
\item All in a single programming language!
\item All in a single program
\item How much work is this?
\end{itemize}
\end{frame}

\begin{frame}[fragile]{Chisel is Productive}
\begin{itemize}
\item All coded and tested in less than 14 hours!
\end{itemize}
\begin{itemize}
\item The hardware in Chisel
\item Assembler in Scala
\item Some assembler programs (blinking LED)
\item Simulation in Scala
\item Two testers
\end{itemize}
\begin{itemize}
\item BUT, this does not include the design (done on paper)
\end{itemize}
\end{frame}


\begin{frame}[fragile]{Goals for this Intro}
\begin{itemize}
\item Get an idea what Chisel is
\begin{itemize}
\item Will show you code snippets
\end{itemize}
\item A first high level view of the main features of Chisel
\item Reconsider how to describe hardware
\item Some experience report from usage at DTU
\item Pointers to more information
\end{itemize}
\end{frame}

%\begin{frame}[fragile]{Talk abstract}
%
%Date: Tu 19/04/2016, 11:00-12:00
%Room: 123/322
%
%Title: Hardware Design in the 21st Century: with the Object Oriented
%and Functional Language Chisel
%
%Chisel is a hardware construction language implemented as a
%domain specific language in Scala. Therefore, the full power of
%a modern programming language is available to describe hardware
%and, more important, hardware generators. Chisel has been developed
%at UC Berkeley and successfully used for several tape outs of RISC-V.
%Here at DTU we used Chisel in the T-CREST project and in teaching
%advanced computer architecture. Besides presenting small code
%examples in Chisel I will report on experiences on using Chisel in
%the t-CREST project and in teaching.
%
%Martin Schoeberl
%\end{frame}

\begin{frame}[fragile]{Chisel}
\begin{itemize}
\item A hardware \emph{construction} language
\begin{itemize}
\item Constructing Hardware In a Scala Embedded Language
\item If it compiles, it is synthesisable hardware 
\item Say goodby to your unintended latches
\end{itemize}
\item Chisel is not a high-level synthesis language
\item Single source two targets
\begin{itemize}
\item Cycle accurate simulation (testing)
\item Verilog for synthesis
\end{itemize}
\item Embedded in Scala
\begin{itemize}
\item Full power of Scala available
\item But to start with, no Scala knowledge needed
\end{itemize}
\item Developed at UC Berkeley
\item Drives the Rocket chip (open-source RISC-V)
\end{itemize}
\end{frame}

\begin{frame}[fragile]{The C Language Family}

\Tree[.C [
   [.{\bf Verilog} {\bf SystemVerilog} ]
   [.C++  \emph{SystemC}  ]
   [.Java [.Scala {\bf Chisel} ] ]
   [.C\# ] ] ]
 
\end{frame}

\begin{frame}[fragile]{Other Language Families}

\begin{columns}
\column{0.5\textwidth}
\begin{center}
\Tree[.Algol [.Ada [.{\bf VHDL} ] ] ]
\end{center}
\column{0.5\textwidth}
\begin{center}
\Tree[.Python [.{\bf MyHDL} ] ]
\end{center}
\end{columns}
\end{frame}

\begin{frame}[fragile]{Some Notes on Scala}
\begin{itemize}
\item Object oriented
\item Functional
\item Strongly typed
\begin{itemize}
\item With very good type inference
\end{itemize}
\item Could be seen as Java++
\item Compiled to the JVM
\item Good Java interoperability
\begin{itemize}
\item Many libraries available
\end{itemize}
\end{itemize}
\end{frame}

\begin{frame}[fragile]{Chisel vs. Scala}
\begin{itemize}
\item A Chisel hardware description is a Scala program
\item Chisel is a Scala library
\item When the program is executed it generates hardware
\item Chisel is a so-called \emph{embedded domain-specific language}
\end{itemize}
\end{frame}

\begin{frame}[fragile]{A Small Language}
\begin{itemize}
\item Chisel is a \emph{small} language
\item On purpose
\item Not many constructs to remember
\item The \href{https://github.com/freechipsproject/chisel-cheatsheet/releases/latest/download/chisel_cheatsheet.pdf}{Chisel Cheatsheet} fits on two pages
\item The power comes with Scala for circuit generators
\item With Scala, Chisel can grow with you
\end{itemize}
\end{frame}

\begin{frame}[fragile]{Expressions are Combinational Circuits}
\begin{chisel}
(a | b) & ~(c ^ d)

val addVal = a + b
val orVal = a | b
val boolVal = a >= b
\end{chisel}
\begin{itemize}
\item The usual operations 
\item Simple name assignment with val
\item Width inference
\item Type inference
\item Types: Bits, UInt, SInt, Bool
\end{itemize}
\end{frame}

\begin{frame}[fragile]{Conditional Updates for Combinational Circuits}
\shortlist{../code/comb_elsewhen.txt}
\begin{itemize}
\item Similar to VHDL \code{process} or SystemVerilog \code{always\_comb}
\item Chisel checks for complete assignments in all branches
\item Latches give compile error
\end{itemize}
\end{frame}

\begin{frame}[fragile]{Registers}
\begin{chisel}
val cntReg = RegInit(0.U(32.W))

cntReg := cntReg + 1.U
\end{chisel}
\begin{itemize}
\item Type inferred by initial value (= reset value)
\item No need to specify a clock or reset signal
\end{itemize}
\begin{itemize}
\item Also definition with an input signal connected:
\end{itemize}
\begin{chisel}
val r = RegNext(nextVal) 
\end{chisel}
\end{frame}

\begin{frame}[fragile]{Functional Abstraction}
\begin{chisel}
  def addSub(add: Bool, a: UInt, b: UInt) =
    Mux(add, a+b, a-b)

  val res = addSub(cond, a, b)
  
  def rising(d: Bool) = d && !RegNext(d)
\end{chisel}
\begin{itemize}
\item Functions for repeated pieces of logic
\item May contain state
\item Functions may return \emph{hardware}
\end{itemize}
\end{frame}


\begin{frame}[fragile]{Bundles}
\begin{chisel}
class DecodeExecute extends Bundle {
  val rs1 = UInt(32.W)
  val rs2 = UInt(32.W)
  val immVal = UInt(32.W)
  val aluOp = new AluOp()
}
\end{chisel}
\begin{itemize}
\item Collection of values in named fields 
\item Like struct or record
\end{itemize}
\end{frame}

\begin{frame}[fragile]{Vectors}
\begin{chisel}
val myVec = Vec(3, SInt(10.W))

myVec(0) := -3.S
val y = myVec(2)
\end{chisel}
\begin{itemize}
\item Indexable vector of elements
\item Bundles and Vecs can be arbitrarily nested
\end{itemize}
\end{frame}

\begin{frame}[fragile]{IO Ports}
\begin{chisel}
class Channel extends Bundle {
  val data = Input(UInt(8.W))
  val ready = Output(Bool())
  val valid = Input(Bool())
}
\end{chisel}
\begin{itemize}
\item Ports are Bundles with directions
\item Direction can also be assigned at instantiation:
\end{itemize}
\begin{chisel}
class ExecuteIO extends Bundle {
  val dec = Input(new DecodeExecute())
  val mem = Output(new ExecuteMemory())
}
\end{chisel}
\end{frame}

\begin{frame}[fragile]{Modules}
\begin{chisel}
class Adder extends Module {
  val io = IO(new Bundle {
    val a = Input(UInt(4.W))
    val b = Input(UInt(4.W))
    val result = Output(UInt(4.W))
  })

  val addVal = io.a + io.b
  io.result := addVal
}
\end{chisel}
\begin{itemize}
\item Organization of components
\item IO ports defined as a Bundle named \code{io} and wrapped into an \code{IO()}
\item Created (instantiated) with:
\end{itemize}
\begin{chisel}
val adder = Module(new Adder())
\end{chisel}
\end{frame}

\begin{frame}[fragile]{Hello World in Chisel}
\shortlist{../code/hello.txt}
\end{frame}

\begin{frame}[fragile]{Tool Flow for Chisel}
\begin{figure}
    \centering
    \includegraphics[scale=0.35]{../figures/flow}
\end{figure}
\end{frame}

% copy of generation and edited
\begin{frame}[fragile]{Chisel has a Multiplexer}
\begin{figure}
  \includegraphics[scale=\scale]{../figures/mux}
\end{figure}
\shortlist{../code/mux.txt}
\begin{itemize}
\item So what?
\item Wait... What type is \code{a} and \code{b}?
\begin{itemize}
\item Can be any Chisel type!
\end{itemize}
\end{itemize}
\end{frame}

\begin{frame}[fragile]{Chisel has a Generic Multiplexer}
\begin{figure}
  \includegraphics[scale=\scale]{../figures/mux}
\end{figure}
\shortlist{../code/mux.txt}
\begin{itemize}
\item SW people may not be impressed
\item They have generics since Java 1.5 in 2004
\begin{itemize}
\item \code{List<Flowers> != List<Cars>}
\end{itemize}
\end{itemize}
\end{frame}


\begin{frame}[fragile]{Generics in Hardware Construction}
\begin{itemize}
\item Chisel supports generic classes with type parameters
\item Write hardware generators independent of concrete type
\item This is a multiplexer \emph{generator}
\end{itemize}
\shortlist{../code/param_func.txt}
\end{frame}

\begin{frame}[fragile]{Put Generics Into Use}
\begin{itemize}
\item Let us implement a generic FIFO
\item Use the generic ready/valid interface from Chisel
\end{itemize}
\shortlist{../code/fifo_decoupled.txt}
\end{frame}

\begin{frame}[fragile]{Define the FIFO Interface}
\shortlist{../code/fifo_io.txt}
\begin{itemize}
\item We need enqueueing and dequeueing ports
\item Note the \code{Flipped}
\begin{itemize}
\item It switches the direction of ports
\item No more double definitions of an interface
\end{itemize}
\end{itemize}
\end{frame}

\begin{frame}[fragile]{But What FIFO Implementation?}
\begin{itemize}
\item Bubble FIFO (good for low data rate)
\item Double buffer FIFO (fast restart)
\item FIFO with memory and pointers (for larger buffers)
\begin{itemize}
\item Using flip-flops
\item Using on-chip memory
\end{itemize}
\item And some more...
\end{itemize}
\begin{itemize}
\item This calls for object-oriented \sout{programming} \emph{hardware construction}
\end{itemize}
\end{frame}

\begin{frame}[fragile]{Abstract Base Class and Concrete Extension}
\shortlist{../code/fifo_abstract.txt}
\begin{itemize}
\item May contain common code
\item Extend by concrete classes
\end{itemize}
\begin{chisel}
class BubbleFifo[T <: Data](gen: T, depth: Int) extends Fifo(gen: T, depth: Int) {
\end{chisel}
\end{frame}



\begin{frame}[fragile]{Select a Concrete FIFO Implementation}
\begin{itemize}
\item Decide at hardware generation
\item Can use all Scala/Java power for the decision
\begin{itemize}
\item Connect to a web service, get \sout{Google} Alphabet stock price, and decide on which to use ;-)
\item For sure a silly idea, but you see what is possible...
\item Developers may find clever use of the Scala/Java power
\item We could present a GUI to the user to select from
\end{itemize}
\item We use XML files parsed at hardware generation time
\item End of TCL, Python,... generated hardware
\end{itemize}
\end{frame}

\begin{frame}[fragile]{Binary to BCD Conversion for VHDL}
\begin{figure}
    \centering
    \includegraphics[scale=0.6]{JavaBCD}
\end{figure}
\end{frame}

\begin{frame}[fragile]{Java Program}
\begin{itemize}
\item Generates a VHDL table
\item The core code is:
\end{itemize}
\begin{chisel}
for (int i = 0; i < Math.pow(2, ADDRBITS); ++i) {
    int val = ((i/10)<<4) + i%10;
    // write out VHDL code for each line
\end{chisel}
\begin{itemize}
\item With all boilerplate 118 LoC
\end{itemize}
\end{frame}

\begin{frame}[fragile]{Chisel Version of Binary to BCD Conversion}
%\begin{chisel}
%  val array = new Array[Int](256)
%  for (i <- 0 to 99) {
%    array(i) = ((i/10)<<4) + i%10
%  }
%  val table = VecInit(array.map(_.U(8.W)))
%\end{chisel}
\begin{chisel}
  val table = Wire(Vec(100, UInt(8.W)))
  for (i <- 0 until 100) {
    table(i) := (((i/10)<<4) + i%10).U
  }
  val bcd = table(bin)
\end{chisel}
\begin{itemize}
\item Directly generates the hardware table as a \code{Vec}
\item At hardware construction time
\item In the same language
\end{itemize}
\end{frame}

\begin{frame}[fragile]{Use Functional Programming for Generators}
\shortlist{../code/fun_first.txt}
\shortlist{../code/fun_func_lit.txt}
\shortlist{../code/fun_reduce_tree.txt}
\begin{itemize}
\item This is a simple example
\item What about an arbitration tree with fair arbitration?
\end{itemize}
\end{frame}




\begin{frame}[fragile]{Chisel in Teaching}
\begin{itemize}
\item Using/offering it in Advanced Computer Architecture
\item Spring 2016--2018, 2020--2022 all projects have been in Chisel
\item Several Bachelor and Master projects
\item Students pick it up reasonable fast
\item For software engineering students easier than VHDL
\item Switch Digital Electronics 2 at DTU to Chisel (spring semester 2020)
\item Issue of \emph{writing a program} instead of describing hardware remains
\end{itemize}
\end{frame}

\begin{frame}[fragile]{Chisel in Digital Electronic 2}
\begin{itemize}
\item Basic RTL level digital design wit Chisel
\item Chisel testers for debugging
\item Very FPGA centric course
\item Final project is a vending machine
\item All material (slides, book, lab material) in open source
\item Tried to coordinate with introduction to programming (Java)
\begin{itemize}
\item But sometimes I was ahead with Chisel constructs (e.g., classes)
\end{itemize}
\end{itemize}
\end{frame}

\begin{frame}[fragile]{Then there was the Lockdown}
\begin{itemize}
\item Usually one FPGA board per group
\item No group meetings
\item Just virtual labs
\item Can I do something about it with Chisel?
\end{itemize}
\end{frame}


\begin{frame}[fragile]{A Chisel Book}
\begin{figure}
    \centering
    \includegraphics[scale=0.4]{../cover-small}
\end{figure}

\begin{itemize}
\item Available in open access (PDF)
\item In paper from Amazon
\item see \url{http://www.imm.dtu.dk/~masca/chisel-book.html}
\item Source at \url{https://github.com/schoeberl/chisel-book}
\end{itemize}
\end{frame}

\begin{frame}[fragile]{What May Happen with an Open-Source Book}
\begin{figure}
    \centering
    \includegraphics[scale=0.4]{../cover-small-chinese}
\end{figure}

\begin{itemize}
\item A free Chinese translation
\end{itemize}
\end{frame}

\begin{frame}[fragile]{Then I got This}
\begin{figure}
    \centering
    \includegraphics[scale=0.4]{../cover-small-jp}
\end{figure}

\begin{itemize}
\item A Japanese translation
\end{itemize}
\end{frame}

\begin{frame}[fragile]{And One More}
\begin{figure}
    \centering
    \includegraphics[scale=0.4]{../cover-small-vi}
\end{figure}

\begin{itemize}
\item A Vietnamese translation
\end{itemize}
\end{frame}

\begin{frame}[fragile]{Further Information}
\begin{itemize}
\item \url{https://github.com/schoeberl/chisel-book}
\item \url{https://github.com/schoeberl/chisel-lab}
\item \url{https://www.chisel-lang.org/}
\item \url{https://github.com/ucb-bar/chisel-tutorial}
\item \url{https://github.com/ucb-bar/generator-bootcamp}
%\item Chisel 2 documentation at \url{https://github.com/schoeberl/chisel2-doc}
%\begin{itemize}
%\item Chisel 2.2 Tutorial
%\item Getting Started with Chisel
%\end{itemize}
\item \url{http://groups.google.com/group/chisel-users}
\end{itemize}
\end{frame}



\begin{frame}[fragile]{Summary}
\begin{itemize}
% \item The world is digital
%\item Processors do not get much faster -- we need to design domain specific hardware accelerators
\item We need a modern language for hardware/systems design
\item Chisel is a small language
\item Embedding it in Scala gives the power
\item Chisel is good for hardware generators
\item Supports agile hardware development
% \item You can get started with a hardware design in a special course or 4th semester project
\item We can do co-simulation
\end{itemize}
\end{frame}

\end{document}

\begin{frame}[fragile]{Title}
\begin{itemize}
\item abc
\end{itemize}
\end{frame}
